M36D0R6040T0ZAIT Datasheet

IC型號(hào)：
M36D0R6040T0ZAIT
PDF描述：
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 M...
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STMICROELECTRONICS

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M36D0R6040T0

M36D0R6040B0

64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory

and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package

FEATURES SUMMARY

MULTI-CHIP PACKAGE

鈥?1 die of 64 Mbit (4Mb x 16) Flash Memory

鈥?1 die of 16 Mbit (1Mb x 16) Pseudo SRAM

鈻?/div>

SUPPLY VOLTAGE

鈥?V

DDF

= V

DDP

= 1.7V to 1.95V

鈻?/div>

LOW POWER CONSUMPTION

鈻?/div>

ELECTRONIC SIGNATURE

鈥?Manufacturer Code: 20h

鈥?Device Code (Top Flash Configuration),

M36D0R6040T0: 8810h

鈥?Device Code (Bottom Flash

Configuration), M36D0R6040B0: 8811h

鈻?/div>

PACKAGE

鈥?Compliant with Lead-Free Soldering

Processes

鈥?Lead-Free Versions

FLASH MEMORY

鈻?/div>

PROGRAMMING TIME

鈥?8碌s by Word typical for Fast Factory

Program

鈥?Double/Quadruple Word Program option

鈥?Enhanced Factory Program options

鈻?/div>

MEMORY BLOCKS

鈥?Multiple Bank Memory Array: 4 Mbit

Banks

鈥?Parameter Blocks (Top location)

鈻?/div>

ASYNCHRONOUS READ

鈥?Asynchronous Page Read mode

鈥?Random Access: 70ns

鈻?/div>

DUAL OPERATIONS

鈥?Program Erase in one Bank while Read in

others

鈥?No delay between Read and Write

operations

鈻?/div>

BLOCK LOCKING

鈥?All blocks locked at Power-up

鈥?Any combination of blocks can be locked

鈥?WP

for Block Lock-Down

鈻?/div>

Figure 1. Package

FBGA

Stacked TFBGA67 (ZAI)

12 x 8mm

SECURITY

鈥?128-bit user programmable OTP cells

鈥?64-bit unique device number

鈻?/div>

COMMON FLASH INTERFACE (CFI)

鈻?/div>

100,000 PROGRAM/ERASE CYCLES per

BLOCK

PSRAM

鈻?/div>

ACCESS TIME: 70ns

鈻?/div>

LOW STANDBY CURRENT: 110碌A(chǔ)

鈻?/div>

DEEP POWER DOWN CURRENT: 10碌A(chǔ)

鈻?/div>

December 2004

1/18

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