128M Synchronous DRAM
SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as
4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is
suitable for main memory or graphic memory in computer systems.
FEATURES
M2V28S20/30/40TP
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Clock Cycle Time
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
Operation Current
(Max.)
(Single Bank)
(Max.)
(Min.)
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V28S20
V28S30
V28S40
Icc6
Self Refresh Current
-6
7.5ns
45ns
20ns
5.4ns
67.5ns
120mA
130mA
-
2mA
-7
10ns
50ns
20ns
6ns
70ns
115mA
120mA
135mA
2mA
-8
10ns
50ns
20ns
6ns
70ns
115mA
120mA
135mA
2mA
Active to Precharge Command Period
- Single 3.3V 鹵0.3V power supply
- Max. Clock frequency
-6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40TP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20TP/30TP/40TP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1