128M Synchronous DRAM
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
Nov. '99
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
MITSUBISHI LSIs
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
SDRAM (Rev. 1.0E)
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized
as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz,
and is suitable for main memory or graphic memory in computer systems.
FEATURES
M2V28S20/30/40ATP
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Clock Cycle Time
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
Operation Current
(Max.)
(Single Bank)
(Max.)
(Min.)
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V28S20
V28S30
V28S40
Icc6
Self Refresh Current
-6
7.5ns
45ns
20ns
5.4ns
67.5ns
100mA
110mA
130mA
2mA
-7
10ns
50ns
20ns
6ns
70ns
95mA
100mA
120mA
2mA
-8
10ns
50ns
20ns
6ns
70ns
95mA
100mA
120mA
2mA
Active to Precharge Command Period
- Single 3.3V 鹵0.3V power supply
- Max. Clock frequency
-6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1