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M29F002B-120XP1TR Datasheet

  • M29F002B-120XP1TR

  • 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory

  • 199.25KB

  • 29頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M29F002T, M29F002NT
M29F002B
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
5V
鹵
10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
FAST PROGRAMMING TIME: 10碌s typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
鈥?Program Byte-by-Byte
鈥?Status Register bits
MEMORY BLOCKS
鈥?Boot Block (Top or Bottom location)
鈥?Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
鈥?Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
鈥?Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
鈥?Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
鈥?Manufacturer Code: 20h
鈥?Device Code, M29F002T: B0h
鈥?Device Code, M29F002NT: B0h
鈥?Device Code, M29F002B: 34h
DESCRIPTION
The M29F002 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single5V V
CC
supply.For Program and
Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
July 1998
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
18
A0-A17
W
E
G
(*) RPNC
M29F002T
M29F002B
M29F002NT
8
DQ0-DQ7
VSS
AI02078C
Note:
* RPNC function is not available for the M29F002NT
1/29

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