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M27256-20F1 Datasheet

  • M27256-20F1

  • NMOS 256K 32K x 8 UV EPROM

  • 65.25KB

  • 9頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M74HC51
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 11ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 1碌A(chǔ)(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 51
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HC51B1R
M74HC51M1R
T&R
M74HC51RM13TR
M74HC51TTR
DESCRIPTION
The M74HC51 is an high speed CMOS DUAL 2
WIDE 2 INPUT AND/OR INVERT GATE
fabricated with silicon gate C
2
MOS technology.
It contains a 2-WIDE 2-INPUT AND/OR INVERT
GATE and a 2-WIDE 3-INPUT
AND/OR
INVERT GATE.
The internal circuit is composed of 3 stages (2
INPUT) or 5 stages (3 INPUT) including buffer
output, which enables high noise immunity and
stable output.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/9

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