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M2080-2087 Datasheet

  • M2080-2087

  • VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

  • 14頁

  • ICSI

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Integrated
Circuit
Systems, Inc.
Preliminary Information
VCSO FEC PLL
WITH
A
UTO
S
WITCH FOR
SONET/OTN
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
M2080/81/82
M2085/86/87
G
ENERAL
D
ESCRIPTION
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
F
EATURES
鈼?/div>
Integrated SAW delay line; Output of 15 to 700 MHz
*
鈼?/div>
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
鈼?/div>
LVPECL clock output (CML and LVDS options available)
鈼?/div>
Pin-selectable PLL divider ratios support FEC ratios
鈥?M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
鈥?M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
鈥?M2082/87: OTU1 (238/255)
and
OTU2 (237/255) De-mapping
28
29
30
31
32
33
34
35
36
M2080
Series
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
1/1
237/255
238/255
Base Input Rate
1
(MHz)
622.0800
666.5143
669.3266
Output Clock
(either output)
MHz
622.08
or
155.52
鈼?/div>
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
鈼?/div>
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
鈼?/div>
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
鈼?/div>
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
鈼?/div>
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
鈼?/div>
Single 3.3V power supply
鈼?/div>
Small 9 x 9 mm SMT (surface mount) package
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by 鈥淢fin鈥?(as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
M2080 Series
NBW
MUX
PLL
Phase
Detector
Loop Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
Ref Sel
0
Rfec
Div
VCSO
1
0
1
LOL Phase
Detector
Mfec Div
Mfin Divider
(1, 4, 8, 32
or
1, 4, 8, 16)
P Divider
(1, 4, 8, 32 or TriState)
Mfec / Rfec Divider
FEC_SEL1:0
FIN_SEL1:0
P_SEL2:0
2
2
3
LUT
Mfin Divider
LUT
P Divider
LUT
Figure 2: Simplified Block Diagram
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
LOL
FOUT
nFOUT
Tri-state
1
2
3
4
5
6
7
8
9
Revised 30Jul2004
鈼?/div>
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
鈼?/div>
Networking & Communications
w w w. i c s t . c o m
鈼?/div>
tel (508) 852-5400

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