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M2051 Datasheet

  • M2051

  • SAW PLL FOR 10GBE 64B/66B FEC

  • 12頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
Preliminary Information
M2050/51/52
SAW PLL
FOR
10G
B
E 64
B
/66
B
FEC
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2050/51/52 is a VCSO (Voltage Controlled SAW
Oscillator) based clock PLL
designed for FEC clock ratio
translation in 10Gb optical systems
such as 10GbE 64b/66b. It supports
both mapping and de-mapping of
64b/66b encoding and FEC
(Forward Error Correction) clock
multiplication ratios. The ratios are pin-selected from
pre-programming look-up tables.
F
EATURES
鈼?/div>
Integrated SAW delay line; Output of 15 to 700 MHz
*
鈼?/div>
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50Hz to 80MHz)
鈼?/div>
Pin-selectable PLL divider ratios support 64b/66b and
FEC encoding/decoding ratios:
鈥?M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC
鈥?M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE
鈥?M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
28
29
30
31
32
33
34
35
36
M2050
M2051
M2052
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
鈼?/div>
Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
鈼?/div>
LVPECL clock output (CML and LVDS options available)
鈼?/div>
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
鈼?/div>
Loss of Lock (LOL) output pin
鈼?/div>
Narrow Bandwidth control input (NBW Pin)
鈼?/div>
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available; performance conforms with
SONET (GR-253) /SDH (G.813) MTIE and TDEV during
reference clock reselection
鈼?/div>
Single 3.3V power supply
鈼?/div>
Small 9 x 9 mm SMT (surface mount) package
Example I/O Clock Frequency Combinations
Using M2050 Mapper PLL
Base Input
Rate (MHz)
1
625.0000
625.0000
644.5313
Mapper Ratio
Mfec / Rfec
(Pin Selectable)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
VCSO* and Base
Output Rate
(MHz)
2
644.5313
669.6429
690.5692
33 / 32
15 / 14
15 / 14
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be base rate divided by 鈥淢fin鈥?
Note 2: Output rate can be base rate divided by 鈥淧鈥?
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2050, 51, 52
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
FEC_SEL1:0
FIN_SEL1:0
P_SEL2:0
2
Phase
Detector
0
1
Rfec
Div
VCSO
Mfec Div
Mfec and Rfec
Divider
LUT
Mfin Divider
(1, 4, 5, 25)
P Divider
Mfin Divider
LUT
P Divider
LUT
(1, 4, 5, 25 or TriState)
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
2
3
Figure 2: Simplified Block Diagram
M2050/51/52 Datasheet Rev 1.0
M2050/51/52 SAW PLL for 10GbE 64b/66b FEC
鈼?/div>
Revised 23Jun2005
Communications Modules
鈼?/div>
Integrated Circuit Systems, Inc.
w w w. i c s t . c o m
鈼?/div>
tel (508) 852-5400

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