Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2020/21
VCSO B
ASED
C
LOCK
PLL
G
ENERAL
D
ESCRIPTION
The M2020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M2020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
28
29
30
31
32
33
34
35
36
M2020
M2021
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
F
EATURES
鈼?/div>
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
鈼?/div>
Output frequencies of 15 to 700 MHz
*
鈼?/div>
LVPECL clock output (CML and LVDS options available)
鈼?/div>
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
鈼?/div>
Loss of Lock (LOL) output pin
鈼?/div>
Narrow Bandwidth control input (NBW pin)
鈼?/div>
Hitless Switching (HS) options with or without Phase
Build-out (PBO) available for SONET (GR-253) /
SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
鈼?/div>
Industrial temperature grade available
鈼?/div>
Single 3.3V power supply
鈼?/div>
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M2020-11-622.0800 or M2021-11-622.0800
Input Reference
Clock
(MHz)
(M2020)
(M2021)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M2020)
(M2021)
Output Clock
(MHz)
19.44 or 38.88
77.76
155.52
622.08
32 or 16
8
4
1
622.08
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2020/21
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL1:0
2
0
1
R Div
(1, 4,
16, 64)
Phase
Detector
VCSO
M Divider
(1, 4, 16, 64)
(1, 4, 8, 32)
or
( 1, 4, 8, 16)
Mfin Div
M / R Divider
LUT
Mfin Divider
LUT
P Divider
LUT
P Divider
FOUT0: 1, 4, 8, 32 or TriState
FOUT1: 1, 4, 8 or TriState
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
FIN_SEL1:0
P_SEL2:0
2
3
Figure 2: Simplified Block Diagram
M2020/21 Datasheet Rev 1.0
M2020/21 VCSO Based Clock PLL
Revised 30Jul2004
鈼?/div>
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
Networking & Communications
鈼?/div>
w w w. i c s t . c o m
鈼?/div>
tel (508) 852-5400
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