Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2006-12A
VCSO B
ASED
FEC C
LOCK
PLL
WITH
H
ITLESS
S
WITCHING
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
APC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2006-12A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
Clock multiplication ratios (including
forward and inverse FEC) are
pin-selected from pre-programming
look-up tables. Includes Hitless
Switching and Phase Build-out to
enable SONET (GR-253) / SDH (G.813) MTIE and
TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater
clock phase change is detected.
This phase-change triggered implementation of HS is
not recommended when using an unstable reference
(more than 1ns jitter pk-to-pk) or when the resulting
phase detector frequency is less than 5MHz.
28
29
30
31
32
33
34
35
36
M2006-12
A
(Top View)
18
17
16
15
14
13
12
11
10
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
F
EATURES
鈼?/div>
Reduced intrinsic output jitter
and
improved power
supply noise rejection
compared to
M2006-12
鈼?/div>
Similar to the
M2006-02A
- and pin-compatible - but
adds Hitless Switching and Phase Build-out functions
鈼?/div>
Includes
APC
pin for Phase Build-out function (for
absorption of the input phase change)
鈼?/div>
Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation
鈼?/div>
Input reference and VCSO frequencies up to 700MHz
(Specify VCSO frequency at time of order)
鈼?/div>
Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
鈼?/div>
Commercial and Industrial temperature grades
鈼?/div>
Single 3.3V power supply
鈼?/div>
Small 9 x 9 mm SMT (surface mount) package
PLL Ratio
1/1
237/255
(inverse FEC)
Figure 1: Pin Assignment
Example I/O Clock Combinations
Using M2006-12A-622.0800
Input Clock (MHz)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
Output Clock (MHz)
622.08
or
155.52
Table 1: Example I/O Clock Combinations Using M2006-12A-622.0800
Using M2006-12A-669.3266
PLL Ratio
237/255
(FEC rate)
1/1
Input Clock (MHz)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
Output Clock (MHz)
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-12A-669.3266
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2006-12
A
APC
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
4
2
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
P0_SEL
P1_SEL
0
Rfec Div
1
Mfec Div
Mfin Div
(1, 4, 8, or 32)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
VCSO
P0 Div
(1 or 4)
FOUT0
nFOUT0
FEC_SEL3:0
FIN_SEL1:0
P1 Div
(1 or 4)
FOUT1
nFOUT1
Figure 2: Simplified Block Diagram
M2006-12A Datasheet Rev 1.0
M2006-12A VCSO Based FEC Clock PLL with Hitless Switching
Revised 28Jul2004
鈼?/div>
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
Networking & Communications
鈼?/div>
w w w. i c s t . c o m
鈼?/div>
tel (508) 852-5400
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