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ESMT

Revision History

Revision 0.1(Dec. 28 1998)

-Original

Revision 0.2(Jan. 29 1999)

-Add page 45 "Packing Dimension"

Revision 0.3(Apr. 20 2000)

-Modify 6 tss from 2 to 1.5ns.(Page 7)

Revision 0.4(May. 09 2001)

- 64ms refresh period (4K cycle) --> 15.6渭s refresh interval (P.1)

- Add Packing Dimension Title 86-LEAD TSOP(II) DRAM(400mil).

- Modify P.39

Revision 1.0(Jun. 08 2001)

- Modify ICC2NS, ICC6, tRDL, tOH spec

Revision 1.1(Oct. 21 2002)

- Add 鈥? spec, Delete -8 spec

Revision 1.2(Nov. 11 2002)

- Modify tCH, tCL spec

Revision 1.3(Dec. 24 2002)

- Delete -5 spec (AC/DC)

Revision 1.4(Jan. 17 2003)

- Modify tRDL to meet currently spec in the market

Revision 1.5(Feb. 17 2003)

- Typing error

Revision 1.6(Oct. 29 2003)

- Modify refresh period.

Revision 1.7(May. 10 2004)

- M12L64322A-6T tRDL=12ns

- M12L64322A-7T tRDL=14ns

Revision 1.8(May. 02 2005)

- Add pb-free to ordering information

- Recommend to add 4096 auto refresh before and after self refresh

Revision 1.9(Nov. 04 2005)

- Modify tCC / tRCD spec

Revision 2.0(Dec. 08 2005)

- Add 鈥?T speed grade

Revision 2.1(Mar. 08 2006)

- Modify Inch Dimension Max. A2 from 0.011 to 0.041

Revision 2.2(Nov. 27 2006)

- Add BGA 90ball 8x13mm package

Revision 2.3(Mar. 02 2007)

- Delete BGA ball name of packing dimensions

M12L64322A

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2007

Revision: 2.3

1/47

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