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M12L128168A-6TG Datasheet

  • M12L128168A-6TG

  • 2M x 16 Bit x 4 Banks Synchronous DRAM

  • 43頁

  • ESMT

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ESMT
SDRAM
M12L128168A
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO.
M12L128168A-5TG
M12L128168A-6TG
M12L128168A-7TG
MAX FREQ. PACKAGE
COMMENTS
200MHz
166MHz
143MHz
TSOP II
TSOP II
TSOP II
Pb-free
Pb-free
Pb-free
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
S SQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
S SQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
1/43

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