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LX256VCFN1003 Datasheet

  • LX256VCFN1003

  • High Performance Interfacing and Switching

  • 531.25KB

  • 72頁

  • LATTICE   LATTICE

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ispGDX2
鈩?/div>
Family
September 2005
Features
Includes
High-
,
Performance
Low-Cost
鈥淓-Series鈥?/div>
High Performance Interfacing and Switching
Data Sheet
鈻?/div>
Two Options Available
鈥?High-performance sysHSI (standard part number)
鈥?Low-cost, no sysHSI (鈥淓-Series鈥?
鈻?/div>
High Performance Bus Switching
鈥?High bandwidth
鈥?Up to 12.8 Gbps (SERDES)
鈥?Up to 38 Gbps (without SERDES)
鈥?Up to 16 (15x10) FIFOs for data buffering
鈥?High speed performance
鈥?f
MAX
= 360MHz
鈥?t
PD
= 3.0ns
鈥?t
CO
= 2.9ns
鈥?t
S
= 2.0ns
鈥?Built-in programmable control logic capability
鈥?I/O intensive: 64 to 256 I/Os
鈥?Expanded MUX capability up to 188:1 MUX
鈻?/div>
sysHSI Blocks Provide up to 16 High-speed
Channels
Serializer/de-serializer (SERDES) included
Clock Data Recovery (CDR) built in
800 Mbps per channel
LVDS differential support
10B/12B support
鈥?Encoding / decoding
鈥?Bit alignment
鈥?Symbol alignment
鈥?8B/10B support
鈥?Bit alignment
鈥?Symbol alignment
鈥?Source Synchronous support
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈻?/div>
sysCLOCK鈩?PLL
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Frequency synthesis and skew management
Clock multiply and divide capability
Clock shifting up to +/-2.35ns in 335ps steps
Up to four PLLs
鈻?/div>
Flexible Programming and Testing
鈥?IEEE 1532 compliant In-System Programmabil-
ity (ISP鈩?
鈥?Boundary scan test through IEEE 1149.1
interface
鈥?3.3V, 2.5V or 1.8V power supplies
鈥?5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
鈻?/div>
sysIO鈩?Interfacing
鈥?LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
standard board interfaces
鈥?SSTL 2/3 Class I and II support
鈥?HSTL Class I, III and IV support
鈥?GTL+, PCI-X for bus interfaces
鈥?LVPECL, LVDS and Bus LVDS differential support
鈥?Hot socketing
鈥?Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
I/Os
GDX Blocks
t
PD
t
S
t
CO
f
MAX
(Toggle)
Max Bandwidth
sysHSI Channels
2
LVDS/Bus LVDS (Pairs)
PLLs
Package
1. Max number of SERDES channels per device * 800Mbps
2. 鈥淓-Series鈥?does not support sysHSI.
3. f
MAX
(Toggle) * maximum I/Os divided by 2.
ispGDX2-128/E
128
8
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
64
2
208-ball fpBGA
ispGDX2-256/E
256
16
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
128
4
484-ball fpBGA
64
4
3.0ns
2.0ns
2.9ns
360MHz
SERDES
1, 2
3
3.2Gbps
11Gbps
4
32
2
100-ball fpBGA
Without SERDES
漏 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13

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