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LTC3831EGN Datasheet

  • LTC3831EGN

  • High Power Synchronous Switching Regulator Controller for DD...

  • 20頁

  • LINER

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LTC3831
High Power Synchronous
Switching Regulator Controller
for DDR Memory Termination
FEATURES
s
s
s
s
s
s
s
s
DESCRIPTIO
s
s
s
s
s
High Power Switching Regulator Controller
for DDR Memory Termination
V
OUT
Tracks 1/2 of V
IN
or External V
REF
No Current Sense Resistor Required
Low Input Supply Voltage Range: 3V to 8V
Maximum Duty Cycle > 91% Over Temperature
Drives All N-Channel External MOSFETs
High Efficiency: Over 95% Possible
Programmable Fixed Frequency Operation:
100kHz to 500kHz
External Clock Synchronization Operation
Programmable Soft-Start
Low Shutdown Current: <10碌A(chǔ)
Overtemperature Protection
Available in 16-Pin Narrow SSOP Package
The LTC
廬
3831 is a high power, high efficiency switching
regulator controller designed for DDR memory termina-
tion. The LTC3831 generates an output voltage equal to
1/2 of an external supply or reference voltage. The LTC3831
uses a synchronous switching architecture with N-chan-
nel MOSFETs. Additionally, the chip senses output cur-
rent through the drain-source resistance of the upper
N-channel FET, providing an adjustable current limit
without a current sense resistor.
The LTC3831 operates with input supply voltage as low as
3V and with a maximum duty cycle of > 91%. It includes a
fixed frequency PWM oscillator for low output ripple
operation. The 200kHz free-running clock frequency can
be externally adjusted or synchronized with an external
signal from 100kHz to above 500kHz. In shutdown mode,
the LTC3831 supply current drops to <10碌A(chǔ).
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s
s
s
DDR SDRAM Termination
SSTL_2 Interface
SSTL_3 Interface
TYPICAL APPLICATIO
5V
V
DDQ
2.5V
MBR0530T1
1碌F
0.1碌F
PV
CC2
V
CC
0.1碌F
SS
0.01碌F
130k
SHDN
C1
33pF
R
C
15k
C
C
1500pF
PV
CC1
TG
I
MAX
LTC3831 I
FB
FREQSET
SHDN
COMP
BG
PGND
GND
R
+
R
鈥?/div>
FB
C
IN
: SANYO POSCAP 6TPB330M
C
OUT
: SANYO POSCAP 4TPB470M
Q1, Q2: SILICONIX Si4410DY
Q2
MBRS340T3
1k
0.1碌F
L
O
1.2碌H
10k
Q1
MBRS340T3
+
C
IN
330碌F
脳2
EFFICIENCY (%)
+
4.7碌F
V
TT
1.25V
鹵6A
C
OUT
470碌F
脳3
+
3831 F01
Figure 1. Typical DDR Memory Termination Application
3831f
U
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
0
1
3
4
2
LOAD CURRENT (A)
5
6
2831 G01
U
U
T
A
= 25擄C
V
IN
= 2.5V
V
OUT
= 1.25V
1

LTC3831EGN 產(chǎn)品屬性

  • LTC3831

  • 100

  • 集成電路 (IC)

  • PMIC - 穩(wěn)壓器 - 專用型

  • -

  • 控制器，DDR

  • 3 V ~ 8 V

  • 1

  • 1.27 V ~ 4 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SSOP（0.154"，3.90mm 寬）

  • 16-SSOP

  • 管件

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