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LPC2378 Datasheet

  • LPC2378

  • Philips Semiconductors [Single-chip 16-bit/32-bit microcont...

  • PHILIPS

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LPC2378
Single-chip 16-bit/32-bit microcontrollers; 512 kB 鏗俛sh with
ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 01 鈥?6 December 2006
Preliminary data sheet
1. General description
The LPC2378 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with 512 kB of embedded
high-speed 鏗俛sh memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical
performance in interrupt service routines and DSP algorithms, this increases performance
up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
The LPC2378 is ideal for multi-purpose serial communication applications. It incorporates
a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with 4 kB of
endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial
Ports (SSP), three I
2
C interfaces, an I
2
S interface, and an External Memory Controller
(EMC). This blend of serial communications interfaces combined with an on-chip 4 MHz
internal oscillator, SRAM of 32 kB, 16 kB SRAM for Ethernet, 8 kB SRAM for USB and
general purpose use, together with 2 kB battery powered SRAM make this device very
well suited for communication gateways and protocol converters. Various 32-bit timers, an
improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO
lines with up to 50 edge and up to four level sensitive external interrupt pins make these
microcontrollers particularly suitable for industrial control and medical systems.
2. Features
I
ARM7TDMI-S processor, running at up to 72 MHz.
I
Up to 512 kB on-chip 鏗俛sh program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
I
32 kB of SRAM on the ARM local bus for high performance CPU access.
I
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
I
8 kB SRAM for general purpose DMA use also accessible by the USB.
I
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip 鏗俛sh with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
I
EMC provides support for static devices such as 鏗俛sh and SRAM as well as off-chip
memory mapped peripherals.
I
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
I
General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial
interfaces, the I
2
S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port,
as well as for memory-to-memory transfers.

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