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LP61L1008A

Preliminary

Features

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

n

Single 3.3V

鹵

10% power supply

n

Access times: 8/10/12 ns (max.)

n

Current: Operating: 160/155/150mA (max.)

Standby:

5mA (max.)

n

Full static operation, no clock or refreshing required

n

All inputs and outputs are directly TTL compatible

n

Center Power/Ground Pin Configuration

n

Common I/O using three-state output

n

Output enable and one chip enable inputs for easy

application

n

Data retention voltage: 2.0V (min.)

n

Available in 32-pin SOJ 300 mil package

General Description

The LP61L1008A is a high speed 1,048,576-bit static

random access memory organized as 131,072 words by

8 bits and operates on a single 3.3V power supply.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

The chip enable input is provided for POWER-DOWN

and device enable and an output enable input is included

for easy interfacing.

Data retention is guaranteed at a power supply voltage

as low as 2.0V.

Pin Configuration

A0

A1

A2

A3

CE

I/O

1

I/O

2

VCC

GND

I/O

3

I/O

4

WE

A4

A5

A6

A7

1

2

3

4

5

32

31

30

29

28

A16

A15

A14

A13

OE

I/O

8

I/O

7

GND

VCC

I/O

6

I/O

5

A12

A11

A10

A9

A8

LP61L1008AS

6

7

8

9

10

11

12

13

14

15

16

27

26

25

24

23

22

21

20

19

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PRELIMINARY

(August, 2001, Version 1.0)

1

AMIC Technology, Inc.

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