lator designed for use with ceramic output capacitors.
an external 10 nF capacitor to the bypass pin.
鈩?/div>
(Vertically Integrated PNP) pro-
cess, the LP2989 delivers superior performance:
Dropout Voltage:
Typically 310 mV
@
500 mA load, and 1
mV
@
100 碌A(chǔ) load.
Ground Pin Current:
Typically 3 mA
@
500 mA load, and
110 碌A(chǔ)
@
100 碌A(chǔ) load.
Sleep Mode:
The LP2989 draws less than 0.8 碌A(chǔ) quiescent
current when shutdown pin is pulled low.
Error Flag:
The built-in error flag goes low when the output
drops approximately 5% below nominal.
Precision Output:
Guaranteed output voltage accuracy is
0.75% (鈥淎鈥?grade) and 1.25% (standard grade) at room
temperature.
For output voltages
<
2V, see LP2989LV datasheet.
Features
n
n
n
n
n
n
n
n
n
n
n
Ultra low dropout voltage
Guaranteed 500 mA continuous output current
Very low output noise with external capacitor
SO-8, Mini SO-8, 8 Lead LLP surface mount packages
<
0.8 碌A(chǔ) quiescent current when shutdown
Low ground pin current at all loads
0.75% output voltage accuracy (鈥淎鈥?grade)
High peak current capability (800 mA typical)
Wide supply voltage range (16V max)
Overtemperature/overcurrent protection
鈭?0藲C to +125藲C junction temperature range
Applications
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n
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Notebook/Desktop PC
PDA/Palmtop Computer
Wireless Communication Terminals
SMPS Post-Regulator
Block Diagram
10133901
VIP
鈩?/div>
is a trademark of National Semiconductor Corporation.
漏 2002 National Semiconductor Corporation
DS101339
www.national.com
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