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LMU112JC50 Datasheet

  • LMU112JC50

  • 12 x 12-bit Parallel Multiplier

  • 6頁(yè)

  • LOGIC

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LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
DESCRIPTION
The
LMU112
is a high-speed, low
power 12-bit parallel multiplier built
using advanced CMOS technology.
The LMU112 is pin and functionally
compatible with Fairchilds鈥檚 MPY112K.
The A and B input operands are
loaded into their respective registers
on the rising edge of the separate
clock inputs (CLK A and CLK B).
Two鈥檚 complement or unsigned
magnitude operands are accommo-
dated via the operand control bit (TC)
which is loaded along with the B
operands. The operands are specified
to be in two鈥檚 complement format
when TC is asserted and unsigned
magnitude when TC is deasserted.
Mixed mode operation is not allowed.
For two鈥檚 complement operands, the
17 most significant bits at the output
of the asynchronous multiplier array
are shifted one bit position to the left.
This is done to discard the redundant
copy of the sign-bit, which is in the
most significant bit position, and
extend the bit precision by one bit.
The result is then truncated to the 16
MSB鈥檚 and loaded into the output
register on the rising edge of CLK B.
The contents of the output register are
made available via three-state buffers
by asserting OE. When OE is de-
asserted, the outputs (R
23-8
) are in the
high impedance state.
FEATURES
u
u
u
u
25 ns Worst-Case Multiply Time
Low Power CMOS Technology
Replaces Fairchild MPY112K
Two鈥檚 Complement or Unsigned
Operands
u
Three-State Outputs
u
Package Styles Available:
鈥?48-pin PDIP
鈥?52-pin PLCC, J-Lead
LMU112 B
LOCK
D
IAGRAM
A
11-0
12
CLK A
CLK B
A REGISTER
TC
B
11-0
12
B REGISTER
24
FORMAT ADJUST
16
RESULT REGISTER
OE
16
R
23-8
Multipliers
1
08/16/2000鈥揕DS.112-K

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