LMH4345, LMH4045, LMH4075 3Gbps, HD, SD, DVB-ASI SDI Dual Serializer / Deserializer (SER/
DES) with Loopthrough and LVDS Interface
ADVANCE INFORMATION
September 4, 2008
LMH4345, LMH4045, LMH4075
3 Gbps, HD, SD, DVB-ASI SDI Dual Serializer / Deserializer
(SER/DES) with Loopthrough and LVDS Interface
General Description
The Dual SER/DES 5:1 Serializer and 1:5 De-serializer pro-
vides four independent high-speed Serial Digital Interface
(SDI) links, two RX and two TX links, compliant with SMPTE
259M C, SMPTE 292M or SMPTE 424M at datarates of 270
Mbps, 1.5 Gbps or 3 Gbps as applicable. The channels also
will support DVB_ASI interfaces, with internal 8b10b coding/
decoding. Built-in programmable serializer and deserializer
signal conditioning blocks improve signal integrity perfor-
mance and allow flexible board layout. The input and output
of the Dual Serdes are designed to interface easily to FPGA/
ASIC devices. Each input or output channel is supported by
5 pairs of high-speed LVDS connections to reduce FPGA pin
count as well as provide better signal integrity and EMI per-
formance. The serializer outputs have integrated cable
drivers which support SMPTE 259M (270 Mb/s), SMPTE
292M, and SMPTE 424M standards with excellent output jitter
performance. Each Deserializer channel has a reclocked
loopthrough output which also has an integrated cable driver.
When paired with a host FPGA the LMH4345 deserializers
automatically detect the incoming data rate and decode the
raw 5-bit data words compliant to any of the supported stan-
dards. The interface between the LMH4345 and the host
FPGA consists of four 5-bit wide LVDS buses (two input and
two output), an LVDS clock per channel and an SMBus inter-
face. No external VCOs or clocks are required. The LMH4345
receivers detect the frequency from the incoming data
stream, generate a clean clock and transmit both clock and
data to the host FPGA. Refer to table 1 for a listing of the
variants of this product offered. National Semiconductor also
offers single serializers and single deserializers as a part of
the FPGA-Attach SER/DES product family.
The FPGA-Attach SER/DES product family is supported by a
suite of IP which allows the design engineer to quickly develop
video applications using the SER/DES products. The product
is packaged in a 100 pin TQFP package.
Key Specifications
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Output compliant with SMPTE 259M-C, SMPTE 292M,
SMPTE 424M and DVB-ASI
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Typical power dissipation: TBD mW (loopthrough
disabled, 3G datarate)
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Jitter Tolerance (Deserializer) 0.6UI
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Output Jitter (Serializers) 0.1 UI
Features
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Two Independent Serializers and Two Independent
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Deserializers
No external VCO or clocks required
Reclocked serial loopthrough with Cable Driver
Integrated Cable Drivers
Powerdown Mode
3.3V SMBus configuration interface
Small 100 Pin TQFP package
Industrial Temperature range:-40擄C to +85擄C
Applications
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SDI interfaces for:
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Video Cameras
DVRs
Video Switchers
Video Editing Systems
TRI-STATE廬 is a registered trademark of National Semiconductor Corporation.
漏 2008 National Semiconductor Corporation
300682
www.national.com
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