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LMC568CN Datasheet

  • LMC568CN

  • Low Power Phase-Locked Loop

  • 6頁(yè)

  • NSC

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LMC568 Low Power Phase-Locked Loop
May 1999
LMC568
Low Power Phase-Locked Loop
General Description
The LMC568 is an amplitude-linear phase-locked loop con-
sisting of a linear VCO, fully balanced phase detectors, and
a carrier detect output. LMCMOS
鈩?/div>
technology is employed
for high performance with low power consumption.
The VCO has a linearized control range of
鹵
30% to allow de-
modulation of FM and FSK signals. Carrier detect is indi-
cated when the PLL is locked to an input signal greater than
26 mVrms. LMC568 applications include FM SCA and TV
second audio program decoders, FSK data demodulators,
and voice pagers.
Features
n
n
n
n
n
n
Demodulates
鹵
15% deviation FM/FSK signals
Carrier Detect Output with hysteresis
Operation to 500 kHz input frequency
Low THD 鈥?0.5% typ. for
鹵
10% deviation
2V to 9V supply voltage range
Low supply current drain
Typical Application
(100 kHz input frequency, refer to notes pg. 3)
DS009135-1
Order Number LMC568CM or LMC568CN
See NS Package Number M08A or N08E
LMCMOS
鈩?/div>
is a trademark of National Semiconductor Corporation.
漏 1999 National Semiconductor Corporation
DS009135
www.national.com

LMC568CN 產(chǎn)品屬性

  • 40

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器

  • -

  • 時(shí)鐘發(fā)生器

  • 是

  • 時(shí)鐘

  • 時(shí)鐘

  • 1

  • 1:1

  • 無(wú)/無(wú)

  • 700kHz

  • 是/無(wú)

  • 2 V ~ 9 V

  • -25°C ~ 125°C

  • 通孔

  • 8-DIP（0.300"，7.62mm）

  • 8-MDIP

  • 管件

  • *LMC568CNLMC568

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