LMC2626 CMOS LDOR Buffer Chip for Row Inversion Flat Panel Display Systems
PRELIMINARY
November 1995
LMC2626
CMOS LDOR Buffer Chip for Row
Inversion Flat Panel Display Systems
General Description
The LMC2626 integrated circuit is specifically developed for
a row inversion TFT FPD system architecture It is designed
only to be used in conjunction with National鈥檚 LM2625
switching regulator chip
Built on National鈥檚 advanced CMOS CS80 process this chip
generates a high-power precision square-wave from a digi-
tal sync signal The chip also contains thermal shutdown
circuitry system shutdown circuitry and a low drop-out volt-
age regulator to generate a 4 2 volt supply from an external-
ly applied reference voltage of 1 227V
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Used in conjunction with LM2625 chip
High output current buffer
Low buffer on resistance
System shutdown control
LDO voltage regulator
LDOR dropout 0 3V maximum at 150 mA
Thermal shutdown short circuit protection
External reference required for LDOR
V
REF
pin converts to a digital pin to shutdown LM2625
Connection Diagram
8-Pin SO
Pin Description
Pin
1
2
3
4
5
6
7
8
Pin Name
V
REF
SD
SYNC
GND
P5V
V
OUT
V
IN
V
SH
Description
1 218V to 1 242V Ext Reference
from LM2625 (see Note 8)
System Shutdown input pin for
LMC2626 and LMC2625
Digital input square wave from FPD
controller
Ground
Precision Regulated
a
5V Supply
Power Buffer Output
FPD System Supply (
a
4 5V to
a
5 5V)
Low Drop-Out Voltage Regulator
Output
TL H 12541 鈥?1
Top View
Ordering Information
Package
8-Pin SO
Temperature Range
b
40 C to
a
85 C
LMC2626IM
NSC
Drawing
M08A
Transport
Media
Rail
Tape and
Reel
C
1996 National Semiconductor Corporation
TL H 12541
RRD-B30M26 Printed in U S A
1
2
3
4
5
6
