LM9647 Color CMOS Image Sensor VGA 68 FPS
ADVANCE INFORMATION
May 2002
LM9647 Color CMOS Image Sensor VGA 68 FPS
General Description
The LM9647 is a high performance, low power, 1/4" VGA CMOS
Active Pixel Sensor capable of capturing color still or motion
images and converting them to a digital data stream.
Excellent image quality is achieved by integrating a high perfor-
mance analog signal processor comprising of a high speed 10
bit A/D convertor, fixed pattern noise elimination circuits and
separate color gain amplifiers . The offset and black level can be
automatically adjusted on chip using a full loop black level com-
pensation circuit.
Furthermore, a programmable smart timing and control circuit
allowing the user maximum flexibility in adjusting integration
time, active window size, gain, frame rate. Various control, tim-
ing and power modes are also provided.
Applications
f
f
f
f
Dual Mode Camera
Digital Still Camera
Security Camera
Machine Vision
Key Specifications
Array Format
Effective Image Area
Optical Format
Pixel Size
Total: 488 x 672
Active: 488 x 648
Total: 2.93mm x 4.03mm
Active: 2.93mm x 3.89 mm
1/4"
6.0碌m x 6.0碌m
8 & 10 Bit Digital
68 frames per second
57 dB
Rolling Reset
0.5%
1.7%
2.5 volts/lux.s
49%
Bayer pattern
32 LCC
3.0V +/-10%
130mW
-10
o
C to 50
o
C
Features
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Master and slave mode operation
f
Progressive scan read out with horizontal and vertical flip
f
Programmable Exposure:
- Master clock divider
- Inter row delay
- Inter frame delay
- Partial frame integration
f
Four channels of digitally programmable analog gain
f
Full automatic servo loop for black level & offset adjustment
on each gain channel
f
Horizontal & vertical sub-sampling (2:1 & 4:2) with averaging
f
Windowing
f
Programmable pixel clock, inter-frame and inter-line delays
f
compatible serial control interface
f
Power on reset & power down mode
I
2
C
Video Outputs
Frame Rate
Dynamic Range
Electronic Shutter
FPN
PRMU
Sensitivity
Fill Factor
Color Mosaic
Package
Single Supply
Power Consumption
Operating Temp
Overall Chip Block Diagram
sclk sda
sadr
resetb
pwd
mclk
APS Array
Row Address
Decoder
Register
Bank
I
2
C Compatible
Serial I/F
POR
Power
Control
clk gen
Master Sensor Controller
snapshot
extsync
Black Level
Compensation
+/-
Horizontal
Register
+/-
+/-
+/-
ch0
ch1
MUX
ch2
ch3
Figure 1. Chip Block Diagram
10 bit A/D
Digital Video
Framer
d[9:0]
pclk
hsync
vsync
Column CDS
漏
2002 National Semiconductor Corporation
www.national.com
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