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LH543601P-25 Datasheet

  • LH543601P-25

  • 256 x 36 x 2 Bidirectional FIFO

  • 361.29KB

  • 43頁

  • SHARP

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LH543601
FEATURES
鈥?/div>
Fast Cycle Times: 20/25/30/35 ns
鈥?/div>
Pin-Compatible and Functionally-Compatible
0.7碌-Technology Replacement for Sharp LH5420
256
脳
36
脳
2 Bidirectional FIFO
FUNCTIONAL DESCRIPTION
The LH543601 contains two FIFO buffers, FIFO #1
and FIFO #2. These operate in parallel, but in opposite
directions, for bidirectional data buffering. FIFO #1 and
FIFO #2 each are organized as 256 by 36 bits. The
LH543601 is ideal either for wide unidirectional applica-
tions or for bidirectional data applications; component
count and board area are reduced.
The LH543601 has two 36-bit ports, Port A and Port B.
Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edge-
sampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH543601 is a fully-static
part.
Conceptually, the port clocks CK
A
and CK
B
are free-
running, periodic 鈥榗lock鈥?waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these 鈥榗lock鈥?wave-
forms
must
be periodic. An 鈥榓synchronous鈥?mode of
operation is possible, in one or both directions, inde-
pendently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic 鈥榗lock鈥?/div>
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for
each
FIFO. The Almost-Full and Almost-Empty flags are pro-
grammable over the entire FIFO depth, but are automat-
ically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Two 256
脳
36-bit FIFO Buffers
Full 36-bit Word Width
Selectable 36/18/9-bit Word Width on Port B
Independently-Synchronized (鈥楩ully-Asynchronous鈥?
Operation of Port A and Port B
Both Ports
鈥?/div>
鈥楽ynchronous鈥?Enable-Plus-Clock Control at
鈥?/div>
R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
鈥?/div>
Synchronous Request/Acknowledge 鈥楬andshake鈥?/div>
Capability; Use is Optional
鈥?/div>
Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
鈥?/div>
Asynchronous Output Enables
鈥?/div>
Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
鈥?/div>
Almost-Full Flag and Almost-Empty Flag are
Programmable
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Mailbox Registers with Synchronized Flags
Data-Bypass Function
Data-Retransmit Function
Automatic Byte Parity Checking
8 mA-I
OL
High-Drive Three-State Outputs with
Built-In Series Resistor
鈥?/div>
TTL/CMOS-Compatible I/O
鈥?/div>
Space-Saving PQFP and TQFP Packages
鈥?/div>
PQFP to PGA Package Conversion
1
NOTE:
1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics鈥?SMT/PGA Generic
Converter model #5853.
廬
This converter maps the LH543601
132-pin PQFP to a generic 13
脳
13, 132-pin PGA (100-mil
pitch). For more information, contact Sharp or ITT Pomona
Electronics at 1500 East Ninth Street, Pomona, CA 91766,
(909) 469-2900.
1

LH543601P-25相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    256 x 36 x 2 Bidirectional FIFO
    SHARP
  • 英文版
    5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...
    INFINEON
  • 英文版
    5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...
    SIEMENS [S...
  • 英文版
    5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED
    INFINEON
  • 英文版
    5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED
    SIEMENS [S...
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP [Sha...
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP [Sha...
  • 英文版
    4K x 9 Parallel-to Serial FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 x 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 1K X 9 FIFO
    SHARP
  • 英文版
    CMOS 2K X 9 FIFO
    SHARP
  • 英文版
    CMOS 4K X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 x 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP

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