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LH540235 Datasheet

  • LH540235

  • 2048 x 18 / 4096 x 18 Synchronous FIFOs

  • 370.38KB

  • 46頁

  • SHARP

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LH540235/45
FEATURES
鈥?/div>
Fast Cycle Times: 20/25/35 ns
鈥?/div>
Pin-Compatible Drop-In Replacements for
IDT72235B/45B FIFOs
2048
脳
18 / 4096
脳
18 Synchronous FIFOs
鈥?/div>
May be Cascaded for Increased Depth, or
Paralleled for Increased Width
鈥?/div>
16 mA-IOL High-Drive Three-State Outputs
鈥?/div>
Five Status Flags: Full, Almost-Full, Half-Full,
Almost-Empty, and Empty; 鈥楢lmost鈥?Flags are
Programmable
鈥?/div>
Choice of IDT-Compatible or
Enhanced
Operating
Mode; Selected by an Input Control Signal
鈥?/div>
Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the
EMODE
Control Input: Programming is Allowed, but
is not Required
鈥?/div>
In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can be Made
Completely Synchronous
鈥?/div>
In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for
36-Bit Data Width, when Selected and
Appropriately Connected
鈥?/div>
Internal Memory Array Architecture Based on CMOS
鈥?/div>
鈥楽ynchronous鈥?Enable-Plus-Clock Control at Both
Input Port and Output Port
Dual-Port SRAM Technology, 2048
脳
18 or 4096
脳
18
鈥?/div>
In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress
Reading
鈥?/div>
Independently-Synchronized Operation of Input Port
and Output Port
鈥?/div>
Control Inputs Sampled on Rising Clock Edge
鈥?/div>
Most Control Signals Assertive-LOW for
Noise Immunity
鈥?/div>
Data Retransmit Function
鈥?/div>
TTL/CMOS-Compatible I/O
鈥?/div>
Space-Saving 68-Pin PLCC Package; Even-Smaller
64-Pin TQFP Package
RS
RESET
LOGIC
FL/
RT
WXI/
WEN
2
WXO/HF
RXI/
REN
2
RXO/
EF
2
EXPANSION
LOGIC
FIFO
MEMORY ARRAY
2048 x 18/4096 x 18
WRITE
POINTER
WCK
WEN
WXI/
WEN
2
READ
POINTER
RCK
OUTPUT
PORT
CONTROL
LOGIC
REN
RXI/
REN
2
INPUT
PORT
CONTROL
LOGIC
FF
PAF
WXO/HF
INPUT
PORT
DEDICATED AND
PROGRAMMABLE
STATUS FLAGS
OUTPUT
PORT
PROGRAMMABLE
REGISTERS
EF
PAE
RXO
/EF
2
OE
Q
0
- Q
17
D
0
- D
17
LD
EMODE
BOLD ITALIC = Enhanced Operating Mode.
540235-1
Figure 1. LH540235/45 Block Diagram
BOLD ITALIC = Enhanced Operating Mode
1

LH540235相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    256 x 36 x 2 Bidirectional FIFO
    SHARP
  • 英文版
    5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...
    INFINEON
  • 英文版
    5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...
    SIEMENS [S...
  • 英文版
    5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED
    INFINEON
  • 英文版
    5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED
    SIEMENS [S...
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP [Sha...
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP
  • 英文版
    Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
    SHARP [Sha...
  • 英文版
    4K x 9 Parallel-to Serial FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 x 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 1K X 9 FIFO
    SHARP
  • 英文版
    CMOS 2K X 9 FIFO
    SHARP
  • 英文版
    CMOS 4K X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP
  • 英文版
    CMOS 512 x 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP [Sha...
  • 英文版
    CMOS 512 X 9 FIFO
    SHARP

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