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LH532100B-1 Datasheet

  • LH532100B-1

  • CMOS 2M (256K x 8) MROM

  • 8頁

  • SHARP

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LH532100B
FEATURES
鈥?/div>
262,144 words
脳
8 bit organization
鈥?/div>
Access time: 150 ns (MAX.)
鈥?/div>
Low-power consumption:
Operating: 275 mW (MAX.)
Standby: 550
碌W
(MAX.)
鈥?/div>
Static operation
鈥?/div>
Mask-programmable OE/OE and
OE
1
/OE
1
/DC
鈥?/div>
TTL compatible I/O
鈥?/div>
Three-state outputs
鈥?/div>
Single +5 V power supply
鈥?/div>
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 450-mil QFJ (PLCC)
32-pin, 8
脳
20 mm
2
TSOP (Type I)
32-pin, 400-mil TSOP (Type II)
鈥?/div>
JEDEC standard EPROM pinout (DIP)
CMOS 2M (256K
脳
8) MROM
DESCRIPTION
The LH532100B is a 2M-bit mask-programmable
ROM organized as 262,144
脳
8 bits. It is fabricated
using silicon-gate CMOS process technology.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
OE
1
/OE
1
/DC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
DC
A
17
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
532100B-1
TOP VIEW
Figure 1. Pin Connections for DIP and
SOP Packages
GND
32-PIN QFJ
D
6
D
5
D
4
D
3
TOP VIEW
D
2
D
1
20 19 18 17 16 15 14
D
7
CE
A
10
OE/OE
A
11
A
9
A
8
A
13
A
14
21
22
23
24
25
26
27
28
29
30 31 32
V
CC
DC
A
17
13
12
11
10
9
8
7
6
5
1
OE
1
/OE
1
/DC
D
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2
A
16
3
A
15
4
A
12
532100B-7
Figure 2. Pin Connections QFJ
(PLCC) Package
1

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