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LF2246QC25 Datasheet

  • LF2246QC25

  • 11 x 10-bit Image Filter

  • 7頁

  • LOGIC

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LF2246
DEVICES INCORPORATED
11 x 10-bit Image Filter
LF2246
DEVICES INCORPORATED
11 x 10-bit Image Filter
DESCRIPTION
The
LF2246
consists of an array of
four 11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. All multiplier inputs
are user accessible and can be up-
dated every clock cycle with either
fractional or integer two鈥檚 comple-
ment data. The pipelined architecture
has fully registered input and output
ports and an asynchronous three-state
output enable control to simplify the
design of complex systems. The
pipeline latency for all inputs is five
clock cycles.
Storage for mixing and filtering
coefficients can be accomplished by
holding the data or coefficient inputs
over multiple clock cycles. A 25-bit
accumulator path allows cumulative
word growth which may be internally
rounded to 16 bits. Output data is
updated every clock cycle and may be
held under user control. All inputs,
outputs, and controls are registered
on the rising edge of clock, except for
OEN. The LF2246 operates at a clock
rate of 66 MHz over the full tempera-
ture and supply voltage ranges.
The LF2246 is applicable for perform-
ing pixel interpolation in image
manipulation and filtering applica-
tions. The LF2246 can perform a
bilinear interpolation of an image (4-
pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.
Unrestricted access to all data and
coefficient input ports provides the
LF2246 with considerable flexibility in
applications such as digital filters,
adaptive FIR filters, mixers, and other
similar systems requiring high-speed
processing.
FEATURES
u
66 MHz Data and Coefficient Input
and Computation Rate
u
Four 11 x 10-bit Multipliers with
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
u
User-Selectable Fractional or
Integer Two鈥檚 Complement Data
Formats
u
Fully Registered, Pipelined Archi-
tecture
u
Input and Output Data Registers,
with User-Configurable Enables
u
Three-State Outputs
u
Fully TTL Compatible
u
Ideally Suited for Image Processing
and Filtering Applications
u
Replaces TRW/Raytheon/Fairchild
TMC2246
u
120-pin PQFPP
LF2246 B
LOCK
D
IAGRAM
D1
9鈥?
ENSEL
C1
10鈥?
ENB1
D2
9鈥?
C2
10鈥?
ENB2
D3
9鈥?
C3
10鈥?
ENB3
D4
9鈥?
C4
10鈥?
ENB4
10
11
10
11
10
11
10
11
22
ACC
25
22
OCEN
FSEL
MS
LS
OEN
CLK
TO ALL REGISTERS
S
15鈥?
Video Imaging Products
2-11
08/16/2000鈥揕DS.2246-K

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