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PIN CONNECTIONS
(top view)
1
DESCRIPTION
These circuits are monolithic J-FET input operational
amplifiers incorporating well matched, high voltage
J-FET on the same chip with standard bipolar transis-
tors.
This amplifiers feature low input bias and offset cur-
rents, low input offset voltage and input offset voltage
drift,coupledwith offsetadjust which doesnot degrade
drift or common-mode rejection.
The devices are also designed for high slew rate, wide
bandwidth,extremelyfastsettlingtime, lowvoltageand
current noise and a low 1/f noise level.
July 1998
8
7
6
5
1
2
3
4
- Offset Null 1
- Inverting input
- Non-inverting input
- V
CC-
5
6
7
8
-
-
-
-
Offset Null 2
Output
+
V
CC
N.C.
2
3
4
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