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LC4256ZE5MN64IES Datasheet

  • LC4256ZE5MN64IES

  • 1.8V In-System Programmable Ultra Low Power PLDs

  • 54頁(yè)

  • LATTICE   LATTICE

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ispMACH 4000ZE Family
1.8V In-System Programmable
Ultra Low Power PLDs
August 2008
Data Sheet DS1022
廬
Features
鈻?/div>
High Performance
鈥?f
MAX
= 260MHz maximum operating frequency
鈥?t
PD
= 4.4ns propagation delay
鈥?Up to four global clock pins with programmable
clock polarity control
鈥?Up to 80 PTs per output
鈻?/div>
Broad Device Offering
鈥?32 to 256 macrocells
鈥?Multiple temperature range support
鈥?Commercial: 0 to 90擄C junction (T
j
)
鈥?Industrial: -40 to 105擄C junction (T
j
)
鈥?Space-saving packages
鈻?/div>
Easy System Integration
鈥?Operation with 3.3V, 2.5V, 1.8V or 1.5V
LVCMOS I/O
鈥?5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
鈥?Hot-socketing support
鈥?Open-drain output option
鈥?Programmable output slew rate
鈥?3.3V PCI compatible
鈥?I/O pins with fast setup path
鈥?/div>
Input hysteresis*
鈥?1.8V core power supply
鈥?IEEE 1149.1 boundary scan testable
鈥?IEEE 1532 ISC compliant
鈥?1.8V In-System Programmable (ISP鈩? using
Boundary Scan Test Access Port (TAP)
鈥?Pb-free package options (only)
鈥?/div>
On-chip user oscillator and timer*
鈻?/div>
Ease of Design
鈥?Flexible CPLD macrocells with individual clock,
reset, preset and clock enable controls
鈥?Up to four global OE controls
鈥?Individual local OE control per I/O pin
鈥?Excellent First-Time-Fit
TM
and re鏗乼
鈥?Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
鈻?/div>
Ultra Low Power
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Standby current as low as 10碌A(chǔ) typical
1.8V core; low dynamic power
Operational down to 1.6V V
CC
Superior solution for power sensitive consumer
applications
鈥?Per pin pull-up, pull-down or bus keeper
control
*
鈥?/div>
Power Guard with multiple enable signals*
*New enhanced features over original ispMACH 4000Z
Table 1. ispMACH 4000ZE Family Selection Guide
ispMACH 4032ZE
Macrocells
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltages (V)
Packages
1
(I/O + Dedicated Inputs)
48-Pin TQFP (7 x 7mm)
64-Ball csBGA (5 x 5mm)
100-Pin TQFP (14 x 14mm)
144-Pin TQFP (20 x 20mm)
144-Ball csBGA (7 x 7mm)
1. Pb-free only.
ispMACH 4064ZE
64
4.7
2.5
3.2
241
1.8V
32+4
48+4
64+10
64+10
ispMACH 4128ZE
128
5.8
2.9
3.8
200
1.8V
ispMACH 4256ZE
256
5.8
2.9
3.8
200
1.8V
32
4.4
2.2
3.0
260
1.8V
32+4
32+4
64+10
96+4
96+4
64+10
96+14
108+4
漏 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
DS1022_01.2

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