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LC4256B-3TN100C Datasheet

  • LC4256B-3TN100C

  • 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density...

  • 99頁

  • LATTICE   LATTICE

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ispMACH 4000V/B/C/Z Family
廬
November 2007
Coolest Power
C
TM
3.3V/2.5V/1.8V In-System Programmable
SuperFAST
TM
High Density PLDs
Data Sheet DS1020
Features
鈻?/div>
High Performance
鈻?/div>
Broad Device Offering
鈥?Multiple temperature range support
鈥?Commercial: 0 to 90擄C junction (T
j
)
鈥?Industrial: -40 to 105擄C junction (T
j
)
鈥?Extended: -40 to 130擄C junction (T
j
)
鈥?For AEC-Q100 compliant devices, refer to
LA-ispMACH 4000V/Z Automotive Data Sheet
鈥?f
MAX
= 400MHz maximum operating frequency
鈥?t
PD
= 2.5ns propagation delay
鈥?Up to four global clock pins with programmable
clock polarity control
鈥?Up to 80 PTs per output
鈻?/div>
Ease of Design
鈥?Enhanced macrocells with individual clock,
reset, preset and clock enable controls
鈥?Up to four global OE controls
鈥?Individual local OE control per I/O pin
鈥?Excellent First-Time-Fit
TM
and re鏗乼
鈥?Fast path, SpeedLocking
TM
Path, and wide-PT
path
鈥?Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
鈻?/div>
Easy System Integration
鈥?Superior solution for power sensitive consumer
applications
鈥?Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
鈥?Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C/Z) supplies
鈥?5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
鈥?Hot-socketing
鈥?Open-drain capability
鈥?Input pull-up, pull-down or bus-keeper
鈥?Programmable output slew rate
鈥?3.3V PCI compatible
鈥?IEEE 1149.1 boundary scan testable
鈥?3.3V/2.5V/1.8V In-System Programmable
(ISP鈩? using IEEE 1532 compliant interface
鈥?I/O pins with fast setup path
鈥?Lead-free package options
鈻?/div>
Zero Power (ispMACH 4000Z) and Low
Power (ispMACH 4000V/B/C)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Typical static current 10碌A(chǔ) (4032Z)
Typical static current 1.3mA (4000C)
1.8V core low dynamic power
ispMACH 4000Z operational down to 1.6V V
CC
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
4032V/B/C
Macrocells
I/O + Dedicated Inputs
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltages (V)
Pins/Package
32
30+2/32+4
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30+2/32+4/
64+10
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64+10/92+4/
96+4
2.7
1.8
2.7
333
3.3/2.5/1.8V
ispMACH
4256V/B/C
256
64+10/96+14/
128+4/160+4
3.0
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4384V/B/C
384
128+4/192+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP
1
100 TQFP
144 TQFP
1
176 TQFP
256 ftBGA
2
/
fpBGA
2, 3
176 TQFP
256 ftBGA/
fpBGA
3
176 TQFP
256 ftBGA/
fpBGA
3
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O con鏗乬urations.
3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.
漏 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
DS1020_23.0

LC4256B-3TN100C 產(chǎn)品屬性

  • 90

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • ispMACH® 4000B

  • 系統(tǒng)內(nèi)可編程

  • 3.0ns

  • 2.3 V ~ 2.7 V

  • 16

  • 256

  • -

  • 64

  • 0°C ~ 90°C

  • 表面貼裝

  • 100-LQFP

  • 100-TQFP（14x14）

  • 托盤

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