鈻?/div>
Easy System Integration
鈥?Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
鈥?Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C) supplies
鈥?Hot-socketing
鈥?Open-drain capability
鈥?Input pull-up, pull-down or bus-keeper
鈥?Programmable output slew rate
鈥?3.3V PCI compatible
鈥?IEEE 1149.1 boundary scan testable
鈥?3.3V/2.5V/1.8V In-System Programmable
(ISP鈩? using IEEE 1532 compliant interface
鈥?I/O pins with fast setup path
鈻?/div>
Ease of Design
鈥?Enhanced macrocells with individual clock,
reset, preset and clock enable controls
鈥?Up to four global OE controls
鈥?Individual local OE control per I/O pin
鈥?Excellent First-Time-Fit
TM
and re鏗乼
鈥?Fast path, SpeedLocking
TM
Path, and wide-PT
path
鈥?Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
鈻?/div>
Low Power
鈥?1.8V core E
2
CMOS
廬
technology
鈥?CMOS design techniques provide low static and
dynamic power
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
4032V/B/C
Macrocells
User I/O Options
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltages (V)
Pins/Package
32
30/32
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30/32/64
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64/92
2.7
1.8
2.7
333
3.3/2.5/1.8V
ispMACH
4256V/B/C
256
64/128/160
3.0
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4384V/B/C
384
128/192
3.5
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4512V/B/C
512
128/208
3.5
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
128 TQFP
100 TQFP
176 TQFP
256 fpBGA*
176 TQFP
256 fpBGA
176 TQFP
256 fpBGA
*128-I/O and 160-I/O con鏗乬urations.
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