Ordering number : EN4327A
Asynchronous Silicon Gate CMOS LSI
LC36256ALL, AMLL-70/85/10/12
256 K (32768 words
脳
8 bits) SRAM
Overview
The LC36256ALL, AMLL are fully asynchronous silicon
gate CMOS static RAMs with a 32768 words
脳
8 bits
configuration.
This series has CE chip enable pin for device
select/nonselect control and an OE output enable pin for
output control, and features high speed as well as low
power dissipation.
Current dissipation is notably reduced during stand-by and
data retention. For these reasons, this series is most suited
for use in systems requiring high speed, low power
consumption and long-term battery backup. Simple
memory capacity expansion is also supported.
Package Dimensions
unit: mm
3012A-DIP28
[LC36256ALL]
Features
鈥?Access time
70 ns (max.)
85 ns (max.)
100 ns (max.)
120 ns (max.)
:
:
:
:
LC36256ALL-70, LC36256AMLL-70
LC36256ALL-85, LC36256AMLL-85
LC36256ALL-10, LC36256AMLL-10
LC36256ALL-12, LC36256AMLL-12
unit: mm
3187-SOP28D
[LC36256AMLL]
SANYO: DIP28
鈥?Low current dissipation
During standby
0.5 碌A(chǔ) (max.) / Ta = 25擄C
1 碌A(chǔ) (max.) / Ta = 0 to +40擄C
5 碌A(chǔ) (max.) / Ta = 0 to +70擄C
During data retention
0.3 碌A(chǔ) (max.) / Ta = 25擄C
0.6 碌A(chǔ) (max.) / Ta = 0 to +40擄C
3 碌A(chǔ) (max.) / Ta = 0 to +70擄C
During operation (DC)
10 mA (max.)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single 5 V power supply: 5 V 鹵10%
Data retention power supply voltage: 2.0 to 5.5 V
No clock required (Fully static memory)
All input/output levels are TTL compatible
Common input/output pins, with three output states
Packages
DIP 28- pin (600 mil) plastic package : LC36256ALL
SOP 28-pin (450 mil) plastic package : LC36256AMLL
SANYO: SOP28D
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
32896HA (OT)/21593JN (OT) No. 4327-1/7
LC36256ALL-12相關(guān)型號PDF文件下載
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