L6919C
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
WITH DYNAMIC VID MANAGEMENT
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2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL
ULTRA FAST LOAD TRANSIENT RESPONSE
INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT FROM 0.800V TO 1.550V WITH
25mV STEPS
DYNAMIC VID MANAGEMENT
0.6% OUTPUT VOLTAGE ACCURACY
10% ACTIVE CURRENT SHARING ACCURACY
DIGITAL 2048 STEP SOFT-START
OVERVOLTAGE PROTECTION
OVERCURRENT PROTECTION REALIZED
dsON
OR A
SENSE RESISTOR
OSCILLATOR EXTERNALLY ADJUSTABLE
AND INTERNALLY FIXED AT 200kHz
POWER GOOD OUTPUT AND INHIBIT
FUNCTION
REMOTE SENSE BUFFER
PACKAGE: SO-28
SO-28
ORDERING NUMBERS:L6919CD
L6919CDTR
APPLICATIONS
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POWER SUPPLY FOR SERVERS AND
WORKSTATIONS
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POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
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DISTRIBUTED POWER SUPPLY
BLOCK DIAGRAM
O SC / I N H
S GN D
DESCRIPTION
The device is a power supply controller specifically de-
signed to provide a high performance DC/DC conver-
sion for high current microprocessors. The device
implements a dual-phase step-down controller with a
180擄 phase-shift between each phase. A precise 5-bit
digital to analog converter (DAC) allows adjusting the
output voltage from 0.800V to 1.550V with 25mV binary
steps managing On-The-Fly VID code changes.
The high precision internal reference assures the se-
lected output voltage to be within 鹵0.6%. The high
peak current gate drive affords to have fast switching
to the external power mos providing low switching
losses.
The device assures a fast protection against load
over current and load over/under voltage. An internal
crowbar is provided turning on the low side mosfet if
an over-voltage is detected. In case of over-current,
the system works in Constant Current mode.
VC C D R
BO O T1
2 PH AS E
O SC IL LATO R
P W M1
L OG IC PW M
A DA PT IV E A NT I
CRO SS CO ND UCT IO N
PG O O D
HS
U
T E1
GA
PH AS E1
C U R R EN T
C OR R EC TI ON
D IGITAL
SOF T-START
LO G IC AN D
P RO TEC TIO N S
CH1
O CP
LS
LGAT E1
ISE N1
VCC
VCC DR
TO TA L
C U R R EN T
C U R R EN T
AVG
CU R REN T
REA DIN G
PG N DS1
PG N D
VID 4
VID 3
VID 2
VID 1
VID 0
D AC
C H 2 OC P
C H 1 OC P
CU R REN T
REA DIN G
PG N DS2
ISE N2
C U R R EN T
C OR R EC TI ON
32 k
3 2k
I
FB
CH2
O CP
FB G
FB R
L OG IC PW M
A DA PT IV E A N T I
CR OSS C ON DU CT IO N
LS
LGAT E2
PH AS E2
HS
U GA TE2
BO O T2
3 2k
P W M2
3 2k
R EMO TE
BU FFE R
ERR OR
A MPL IF IER
Vc c
V SEN
FB
CO M P
V cc
December 2002
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