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L4C381JC20 Datasheet

  • L4C381JC20

  • 16-bit Cascadable ALU

  • 87.00KB

  • 12頁

  • LOGIC

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L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
DESCRIPTION
The
L4C381
is a flexible, high speed,
cascadable 16-bit Arithmetic and
Logic Unit. It combines four 381-type
4-bit ALUs, a look-ahead carry
generator, and miscellaneous interface
logic 鈥?all in a single 68-pin package.
While containing new features to
support high speed pipelined architec-
tures and single 16-bit bus configura-
tions, the L4C381 retains full perform-
ance and functional compatibility with
the bipolar 鈥?81 designs.
The L4C381 can be cascaded to
perform 32-bit or greater operations.
See 鈥淐ascading the L4C381鈥?toward
the end of this data sheet for more
information.
ARCHITECTURE
The L4C381 operates on two 16-bit
operands (A and B) and produces a
16-bit result (F). Three select lines
control the ALU and provide 3
arithmetic, 3 logical, and 2 initializa-
tion functions. Full ALU status is
provided to support cascading to
longer word lengths. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal
feedback path allows the registered
ALU output to be routed to one of the
ALU inputs, accommodating chain
operations and accumulation. Fur-
thermore, the A or B input can be
forced to Zero allowing unary func-
tions on either operand.
ALU OPERATIONS
FTAB
FEATURES
u
High-Speed (15ns), Low Power
16-bit Cascadable ALU
u
Implements Add, Subtract, Accumu-
late, Two鈥檚 Complement, Pass, and
Logic Operations
u
All Registers Have a Bypass Path
for Complete Flexibility
u
68-pin PLCC, J-Lead
L4C381 B
LOCK
D
IAGRAM
A
15
-A
0
16
B
15
-B
0
16
ENA
A REGISTER
B REGISTER
ENB
0
0
2
The S
2
鈥揝
0
lines specify the operation
to be performed. The ALU functions
and their select codes are shown in
Table 1.
The two functions, B minus A and
A minus B, can be achieved by setting
the carry input of the least significant
slice and selecting codes 001 and 010
respectively.
OSA
OSB
P, G, C
16
OVF, Z
5
4
ALU
16
S
2
-S
0
, C
0
T
ABLE
1.
RESULT REGISTER
ENF
A
LU
F
UNCTIONS
FUNCTION
CLEAR (F = 00
鈥?鈥?鈥?/div>
00)
NOT(A) + B
A + NOT(B)
A+B
A XOR B
A OR B
A AND B
PRESET (F = 11
鈥?鈥?鈥?/div>
11)
S
2
-S
0
000
001
FTF
16
OE
16
010
011
100
101
110
111
CLK
TO ALL REGISTERS
F
15
-F
0
Arithmetic Logic Units
1
08/16/2000鈥揕DS.381-P

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