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KK74LV573N Datasheet

  • KK74LV573N

  • Octal D-type transparent latch (3-State)

  • 8頁(yè)

  • KODENSHI

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TECHNICAL DATA
Octal D-type transparent latch (3-State)
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate D-
type inputs for each latch and 3-State outputs for bus oriented applications.
A latch enable (LE) input and an output enable (OE) input are common to
all internal latches.
The 鈥?73鈥?consists of eight D-type transparent latches with 3-State true
outputs. When LE is HIGH, data at the D n inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will change each
time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at
the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the
outputs. When OE is HIGH, the outputs go to the high impedance OFF-
state. Operation of the OE input does not affect the state of the latches.
The 鈥?73鈥?is functionally identical to the 鈥?63鈥?and the 鈥?73鈥? but the
鈥?63鈥?has inverted outputs and the 鈥?73鈥?has a different pin arrangement.
KK74LV573
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
KK74LV573N
Plastic DIP
KK74LV573DW
SOIC
T
A
= -40擄 to 125擄 C for all packages
鈥?/div>
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
鈥?/div>
Supply voltage range: 1.0 to 5.5 V
鈥?/div>
Low input current: 1.0
碌袗;
0.1
碌袗
at
孝
= 25
擄小
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
L
L
Output
D
H
L
Clock
Q
H
L
no
change
Z
PIN 20=V
CC
PIN 10 = GND
L
H
L,H,
X
X
X
H= high level
L = low level
X = don鈥檛 care
Z = high impedance
1

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