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KK74LV373DW Datasheet

  • KK74LV373DW

  • Octal D-type transparent latch; 3-state

  • 6頁(yè)

  • KODENSHI

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TECHNICAL DATA
Octal D-type transparent latch;
3-state
The
KK74LV373
is a low-voltage Si-gate CMOS devise and is pin and
function compatible with 74HCT373.
The
KK74LV373
is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-state outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE) input
are common to all intemal latches.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 1.2 to 3.6 V
Low Input Current: 1.0
碌A(chǔ)
High Noise Immunity Characteristic of CMOS Devices
KK74LV373
ORDERING INFORMATION
KK74LV373N
Plastic
KK74LV373DW
SOIC
T
A
= -40擄 to 125擄 C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
OE
01
20
19
18
17
16
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
03
04
07
08
13
14
17
18
02
05
06
09
12
15
16
19
V
CC
Q
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
0
02
D
0
03
D
1
04
Q
1
05
Q
2
06
D
2
07
D
3
08
Q
3
09
GND
10
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
LE
373
15
14
13
12
11
LE
OE
11
01
FUNCTION TABLE
PIN 20=V
CC
PIN 10 = GND
Inputs
OE
L
L
L
H
LE
H
H
L
X
Dn
H
L
X
X
Output
Qn
H
L
Qo
Z
X = Don鈥檛 care
Z = High impedance OFF-state
L = Low voltage level
H= HIGH voltage level
1

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