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KK74LV273DW Datasheet

  • KK74LV273DW

  • Octal D Flip-Flop with Common Clock and Reset

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TECHNICAL DATA
Octal D Flip-Flop with Common Clock and Reset
The
KK74LV273
is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The
KK74LV273
has eight edge-triggered, D-type flip-flops with individual
D inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip-flops simultaneously. The state of each
D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop. All outputs
will be forced LOW independently of clock or data inputs by a LOW
voltage level on the MR input. The device is useful for applications where
the true output only is required and the clock and master reset are common
to all storage elements.
鈥?/div>
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
鈥?/div>
Supply voltage range: 1.2 to 5.5 V
鈥?/div>
Low input current: 1.0
碌袗;
0.1
碌袗
at
孝
= 25
擄小
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
KK74LV273
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
KK74LV273N
Plastic DIP
KK74LV273DW
SOIC
T
A
= -40擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
RESET
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
FUNCTION TABLE
Inputs
Reset
L
H
H
PIN 20=V
CC
PIN 10 = GND
Output
D
X
H
L
Clock
X
Q
L
H
L
no change
no change
H
H
L
X
X
H= high level
L = low level
X = don鈥檛 care
Z = high impedance
1

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