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KK74HCT373AN Datasheet

  • KK74HCT373AN

  • Octal 3-State Noninverting Transparent Latch

  • 319.78KB

  • 6頁

  • KODENSHI

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TECHNICAL DATA
KK74HCT373A
Octal 3-State Noninverting
Transparent Latch
The KK74HCT373A may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
The KK74HCT373A is identical in pinout to the LS/ALS373.
The eight latches of the KK74HCT373A are transparent D-type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold times
becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high-impedance state.
Thus, data may be latched even when the outputs are not enabled.
鈥?/div>
TTL/NMOS-Compatible Input Levels
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 4.5 to 5.5 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
ORDERING INFORMATION
KK74HCT373AN Plastic
KK74HCT373ADW SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
PIN 20=V
CC
PIN 10 = GND
L
L
L
H
Latch
Enable
H
H
L
X
D
H
L
X
X
Output
Q
H
L
No Change
Z
X = Don鈥檛 Care
Z = High Impedance
1

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