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KK74HC574AN Datasheet

  • KK74HC574AN

  • Octal 3-State Noninverting D Flip-Flop High-Performance Sili...

  • 6頁

  • KODENSHI

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TECHNICAL DATA
KK74HC574A
Octal 3-State
Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC DIP
The KK74HC574A is identical in pinout to the LS/ALS574. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The OE input does not affect the states of the flip-flops,
but when OE is high, all device outputs are forced to the high-impedance
state; thus, data may be stored even when the outputs are not enabled.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
碌A(chǔ)
High Noise Immunity Characteristic of CMOS Devices
20
1
20
1
DW SUFFIX
SOIC
ORDERING INFORMATION
KK74HC574AN
Plastic DIP
KK74HC574ADW
SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
OE
D0
D1
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
2
3
4
5
6
7
8
9
11
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
D2
D3
D4
D5
D6
D7
GND
FUNCTION TABLE
Inputs
Output
D
H
L
L,H,
X
1
OE
OE
L
Clock
Q
H
L
no
change
Z
PIN 20=V
CC
PIN 10 = GND
L
L
H
X
X
H= high level
L = low level
X = don鈥檛 care
Z = high impedance
1

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