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KK74HC533A Datasheet

  • KK74HC533A

  • Octal 3-State Inverting Transparent Latch

  • 345.36KB

  • 7頁(yè)

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TECHNICAL DATA
KK74HC533A
Octal 3-State Inverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The KK74HC533A is identical in pinout to the LS/ALS533. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears as the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 2.0 to 6.0 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC533AN Plastic
KK74HC533ADW SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
L
PIN 20=V
CC
PIN 10 = GND
L
L
Latch
Enable
H
H
L
D
H
L
X
X
Output
Q
L
H
no
change
Z
H
X
X = don鈥檛 care
Z = high impedance
1

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