KK74HC192A Datasheet

IC型號：
KK74HC192A
PDF描述：
Presettable BCD/Decade UP/DOWN Counter High-Performance Sili...
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430.97KB
PDF頁數(shù)：
8頁
芯片廠家：
KODENSHI

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TECHNICAL DATA

KK74HC192A

Presettable BCD/Decade UP/DOWN Counter

High-Performance Silicon-Gate CMOS

The KK74HC192A is identical in pinout to the LS/ALS192. The

device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

The counter has two separate clock inputs, a Count Up Clock and

Count Down Clock inputs. The direction of counting is determined by

which input is clocked. The outputs change state synchronous with the

LOW-to-HIGH transitions on the clock inputs. This counter may be

preset by entering the desired data on the P0, P1, P2, P3 input. When the

Parallel Load input is taken low the data is loaded independently of either

clock input. This feature allows the counters to be used as devide-by-n by

modifying the count lenght with the preset inputs. In addition the counter

can also be cleared. This is accomplished by inputting a high on the

Master Reset input. All 4 internal stages are set to low independently of

either clock input.Both a Terminal Count Down (TC

) and Terminal

Count Up (TC

) Outputs are provided to enable cascading of both up and

down counting functions. The TC

output produces a negative going

pulse when the counter underflows and TC

outputs a pulse when the

counter overflows. The counter can be cascaded by connecting the TC

and TC

outputs of one device to the Count Up Clock and Count Down

Clock inputs, respectively, of the next device.

鈥?/div>

Outputs Directly Interface to CMOS, NMOS, and TTL

鈥?/div>

Operating Voltage Range: 2.0 to 6.0 V

鈥?/div>

Low Input Current: 1.0

碌A(chǔ)

鈥?/div>

High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

KK74HC192AN Plastic

KK74HC192AD SOIC

= -55擄 to 125擄 C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16 =V

PIN 8 = GND

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KK74HC192A Datasheet

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