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KK74HC175A Datasheet

  • KK74HC175A

  • Quad D Flip-Flop with Common Clock and Reset High-Performanc...

  • 6頁(yè)

  • KODENSHI

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TECHNICAL DATA
KK74HC175A
Quad D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The KK74HC175A is identical in pinout to the LS/ALS175. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is asynchronous
and occurs when a low level is applied to the Reset input. Information at a
D input is transferred to the corresponding Q output on the next positive-
going edge of the Clock input.
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 2.0 to 6.0 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC175AN Plastic
KK74HC175AD SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Reset
PIN 16=V
CC
PIN 8 = GND
L
H
H
H
X = Don鈥檛 care
L
Clock
X
D
X
H
L
X
Outputs
Q
L
H
L
Q
H
L
H
no change
1

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