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KK74HC112AN Datasheet

  • KK74HC112AN

  • Dual J-K Flip-Flop with Set and Reset High-Performance Silic...

  • 321.76KB

  • 6頁

  • KODENSHI

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TECHNICAL DATA
KK74HC112A
Dual J-K Flip-Flop
with Set and Reset
High-Performance Silicon-Gate CMOS
The KK74HC112A is identical in pinout to the LS/ALS112. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 2.0 to 6.0 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
鈥?/div>
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC112AN Plastic
KK74HC112AD SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
H
H
Reset
H
L
L
H
H
H
H
H
H
H
L
H
Clock
X
X
X
J
X
X
X
L
L
H
H
X
X
X
K
X
X
X
L
H
L
H
X
X
X
Outputs
Q
H
L
L
*
L
H
Q
L
H
L
*
H
L
No Change
Toggle
No Change
No Change
No Change
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don鈥檛 Care
1

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