TECHNICAL DATA
KK74ACT175
Quad D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
The KK74ACT175 is identical in pinout to the LS/ALS175,
HC/HCT175. The KK74ACT175 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is asynchronous
and occurs when a low level is applied to the Reset input. Information at a
D input is transferred to the corresponding Q output on the next positive-
going edge of the Clock input.
鈥?/div>
TTL/NMOS Compatible Input Levels
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 4.5 to 5.5 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ);
0.1
碌A(chǔ)
@ 25擄C
鈥?/div>
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT175N Plastic
KK74ACT175D SOIC
T
A
= -40擄 to 85擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Reset
PIN 16=V
CC
PIN 8 = GND
L
H
H
H
X = Don鈥檛 care
L
Clock
X
D
X
H
L
X
Outputs
Q
L
H
L
Q
H
L
H
no change
1
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