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KK74ACT112N Datasheet

  • KK74ACT112N

  • Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gat...

  • 387.42KB

  • 6頁

  • KODENSHI

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TECHNICAL DATA
KK74ACT112
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The KK74ACT112 is identical in pinout to the LS/ALS112,
HC/HCT112. The KK74ACT112 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
鈥?/div>
TTL/NMOS Compatible Input Levels
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 4.5 to 5.5 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ);
0.1
碌A(chǔ)
@ 25擄C
鈥?/div>
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT112N Plastic
KK74ACT112D SOIC
T
A
= -40擄 to 85擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
Reset
H
L
L
H
H
H
H
H
H
H
L
H
Clock
X
X
X
J
X
X
X
L
L
H
H
X
X
X
K
X
X
X
L
H
L
H
X
X
X
Outputs
Q
H
L
L
*
L
H
Q
L
H
L
*
H
L
No Change
Toggle
No Change
No Change
No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don鈥檛 Care
1

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