TECHNICAL DATA
KK74AC109
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The KK74AC109 is identical in pinout to the LS/ALS109,HC/HCT109.
The device inputs are compatible with standard CMOS outputs, with
pullup resistors, they are compatible with LS/ALS outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
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Operating Voltage Range: 2.0 to 6.0 V
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Low Input Current: 1.0
碌A;
0.1
碌A
@ 25擄C
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High Noise Immunity Characteristic of CMOS Devices
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Outputs Source/Sink 24 mA
ORDERING INFORMATION
K
KK74AC109N Plastic
KK74AC109D SOIC
T
A
= -40擄 to 85擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
Reset
H
L
L
H
H
H
H
Clock
X
X
X
J
X
X
X
L
H
L
H
K
X
X
X
L
L
H
H
Outputs
Q
H
L
H
*
L
Q
L
H
H
*
H
Toggle
No Change
H
L
H
H
L
X X
No Change
X = Don鈥檛 care
*
Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
1
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