K4X56163PE-L(F)G
16M x16 Mobile DDR SDRAM
FEATURES
Mobile-DDR SDRAM
鈥?1.8V power supply, 1.8V I/O power
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe(DQS)
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 array )
- Internal Temperature Compensated Self Refresh
- Driver strength ( 1, 1/2, 1/4, 1/8 )
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
鈥?Data I/O transactions on both edges of data strobe, DM for masking.
鈥?Edge aligned data output, center aligned data input.
鈥?No DLL; CK to DQS is not synchronized.
鈥?LDM/UDM for write masking only.
鈥?7.8us auto refresh duty cycle.
鈥?CSP package.
Operating Frequency
DDR200
Speed @CL3
*CL : CAS Latency
DDR133
66Mhz
100Mhz
Column address configuration
Organization
16Mx16
DM is internally loaded to match DQ and DQS identically.
Row Address
A0 ~ A12
Column Address
A0-A8
1
March 2004