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K4S161622D-TC/L10 Datasheet

  • K4S161622D-TC/L10

  • 512K x 16Bit x 2 Banks Synchronous DRAM

  • 1075.75KB

  • 41頁

  • SAMSUNG   SAMSUNG

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K4S161622D
512K x 16Bit x 2 Banks Synchronous DRAM
FEATURES
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3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle (2K/32ms)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG鈥瞫 high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
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ORDERING INFORMATION
Part NO.
K4S161622D-TC/L55
K4S161622D-TC/L60
K4S161622D-TC/L70
K4S161622D-TC/L80
K4S161622D-TC/L10
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
LVTTL
50
TSOP(II)
Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
Bank Select
Refresh Counter
LDQM
Output Buffer
Row Decoder
Sense AMP
512K x 16
Row Buffer
DQi
Address Register
CLK
ADD
512K x 16
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.

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