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JM38510/36101SEA Datasheet

  • JM38510/36101SEA

  • 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

  • 561.00KB

  • 19頁

  • TI

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SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A 鈥?OCTOBER 1976 鈥?REVISED JUNE 1999
D
D
D
D
D
3-State Outputs Interface Directly With
System Bus
Gated Output-Control LInes for Enabling or
Disabling the Outputs
Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
鈥?Parallel Load
鈥?Do Nothing (Hold)
For Application as Bus Buffer Registers
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
TYPE
鈥?73
鈥橪S173A
TYPICAL
PROPAGATION
DELAY TIME
23 ns
18 ns
MAXIMUM
CLOCK
FREQUENCY
35 MHz
50 MHz
SN54173, SN54LS173A . . . J OR W PACKAGE
SN74173 . . . N PACKAGE
SN74LS173A . . . D or N PACKAGE
(TOP VIEW)
M
N
1Q
2Q
3Q
4Q
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLR
1D
2D
3D
4D
G2
G1
SN54LS173A . . . FK PACKAGE
(TOP VIEW)
N
M
NC
V
CC
description
9 10 11 12 13
The 鈥?73 and 鈥橪S173A 4-bit registers include
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or relatively low-impedance loads. The
NC 鈥?No internal connection
high-impedance third state and increased
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
1Q
2Q
NC
3Q
4Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
CLR
1D
2D
NC
3D
4D
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
鈥?5擄C to 125擄C. The SN74173 and SN74LS173A are characterized for operation from 0擄C to 70擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
CLK
GND
NC
G1
G2
1

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