鈥?/div>
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
SN54F109 . . . J PACKAGE
SN74F109 . . . D OR N PACKAGE
(TOP VIEW)
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and trying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
The SN54F109 is characterized for operation over
the full military temperature range of 鈥?55擄C to
125擄C. The SN74F109 is characterized for
operation from 0擄C to 70擄C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
鈫?/div>
鈫?/div>
鈫?/div>
鈫?/div>
L
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
H
Q0
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
SN54F109 . . . FK PACKAGE
(TOP VIEW)
1J
1CLR
NC
1K
1CLK
NC
1PRE
1Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
V
CC
2CLR
2J
2K
NC
2CLK
2PRE
NC 鈥?No internal connection
OUTPUTS
Q
H
L
H鈥?/div>
L
Toggle
Q0
Q0
L
Q0
Q
L
H
H鈥?/div>
H
鈥?The output levels are not guaranteed to meet the minimum
levels for VOH. Furthermore, this configuration is nonstable;
that is, it will not persist when PRE or CLR returns to its
inactive (high) level.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1Q
GND
NC
2Q
2Q
2鈥?
JM38510/34102B2A 產(chǎn)品屬性
0現(xiàn)貨3,252Factory
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