The documentation and process conversion
measures necessary to comply with this
revision shall be completed by 31 October 2001.
INCH-POUND
MIL-PRF-19500/455D
31 July 2001
SUPERSEDING
MIL-PRF-19500/455C
25 January 1998
PERFORMANCE SPECIFICATION
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, POWER SWITCHING,
TYPES 2N5664, 2N5665, 2N5666, 2N5666S, 2N5666U3, 2N5667, AND 2N5667S,
JAN, JANTX, JANTXV, JANS, JANHC, AND JANKC
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, power transistors for use in
high-speed power-switching applications. Four levels of product assurance are provided for each encapsulated
device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for each unencapsulated
device type as specified in MIL-PRF-19500.
1.2 Physical dimensions. See figure 1 (TO-66), figure 2 (TO-5), figure 3 (surface mount), and figure 4 (JANHC,
JANKC).
1.3 Maximum ratings.
Type
P
T
T
A
= +25擄C
P
T
T
C
= +100擄C
V
CBO
V
CEO
V
EBO
I
C
I
B
T
stg
and T
op
W
2N5664
2N5665
2N5666, S, U3
2N5667, S
2.5
2.5
1.2
1.2
(1)
(1)
(3)
(3)
W
30
30
15
15
(2)
(2)
(4)
(4)
V dc
250
400
250
400
V dc
200
300
200
300
V dc
6
6
6
6
A dc
5
5
5
5
A dc
1
1
1
1
擄C
-65 to +200
-65 to +200
-65 to +200
-65 to +200
(1)
(2)
(3)
(4)
Derate linearly 14.3 mW/擄C for T
A
> +25擄C.
Derate linearly 300 mW/擄C for T
C
> +100擄C .
Derate linearly 6.9 mW/擄C for T
A
> +25擄C.
Derate linearly 150 mW/擄C for T
C
> +100擄C .
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in
improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC,
P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD
Form 1426) appearing at the end of this document or by letter.
AMSC N/A
DISTRIBUTION STATEMENT. Approved for public release; distribution is unlimited.
FSC 5961