The documentation and process conversion
measures necessary to comply with this revision
shall be completed by 25 June 2002.
INCH-POUND
MIL-PRF-19500/253H
25 March 2002
SUPERSEDING
MIL-PRF-19500/253G
23 April 2001
PERFORMANCE SPECIFICATION
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, LOW-POWER
TYPES 2N930 AND 2N930UB JAN, JANTX, JANTXV, JANS, JANHC AND JANKC
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN silicon, low-power transistors. Four
levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Two levels of product
assurance are provided for die.
1.2 Physical dimensions. See figure 1 (TO-18), figure 2 (UB, surface mount), and figures 3 and 4 (die).
* 1.3 Maximum ratings. Unless otherwise specified, TC = +25擄C.
PT (1)
TA = +25擄C
mW
360
VCBO
VCEO
VEBO
IC
TJ and TSTG
R
胃JC
擄C/W
97
R
胃JA
擄C/W
485
V dc
60
V dc
45
V dc
6
mA dc
30
擄C
-65 to +200
(1) Derate linearly at 2.06 mW/擄C above TA = +25擄C.
1.4 Primary electrical characteristics.
hFE1 (1)
hFE2 (1)
Cobo
|hfe|
VBE(SAT) (1)
VCE(SAT) (1)
Limits
VCE = 5 V dc
IC = 10 碌A(chǔ) dc
VCE = 5 V dc
IC = 500 碌A(chǔ) dc
VCB = 5 V dc
IE = 0
100 kHz
鈮?/div>
f
鈮?/div>
1 MHz
pF
VCE = 5 V dc
IC = 500 碌A(chǔ) dc
f = 30 MHz
IC = 10 mA dc
IB = 0.5 mA dc
IC = 10 mA dc
IB = 0.5 mA dc
V dc
1.5
6.0
0.6
1.0
V dc
Min
Max
100
300
150
8.0
1.0
(1) Pulsed (see 4.5.1).
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in
improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC/VAC, Post
Office Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD
Form 1426) appearing at the end of this document or by letter.
AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
FSC 5961
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